The CMOS Inverter: It Flips Yet Spends Almost No Power
Sweep the input and catch the moment the output flips
The curve plots the output voltage Vout against the input voltage Vin, which is called the transfer characteristic. As you move the input from 0 to Vdd, the output stays pinned to the upper rail at low inputs, drops steeply near half the supply voltage, and settles at the bottom for high inputs. The faint red hump is the shoot-through current that flows only during the transition, and the two names written on the curve show which transistor is on in each stretch.
A complementary pair, PMOS above, NMOS below
A CMOS inverter pairs two kinds of MOSFET, one above the other. The PMOS on top has its source tied to the supply Vdd, and the NMOS below has its source tied to ground. The two gates are joined at the input, and the two drains are joined at the output. The two are complementary. The NMOS turns on when its gate is high and the PMOS turns on when its gate is low, so they always respond oppositely to the same input. Holes in a PMOS move more slowly than electrons in an NMOS, so the PMOS is usually made wider so that both sides pull with equal strength. Balanced this way, the output flips near half the supply voltage.
Input 0 gives output 1, input 1 gives output 0
When the input is low (0), the NMOS gate voltage falls short of the threshold and it turns off, while the PMOS gate sits well below the supply and it turns on. The PMOS that is on ties the output firmly to the supply, so the output is high (1). When the input is high (1), the opposite happens: only the NMOS turns on and ties the output to ground, so the output is low (0). Either way, the device that is on pulls the output onto one rail, and the output is a clean inversion of the input.
Static power is nearly 0
Here lies the key to CMOS. In any stable state, exactly one of the two transistors is fully off, so there is no current path running straight from the supply to ground. With no static current, an idle gate uses almost no power. Current flows only during the brief moment the input changes, and what flows then is the shoot-through current while both devices are briefly on, plus the current that charges and discharges the load capacitance on the output. So power is spent only when switching, and the dynamic power P ∝ C Vdd² f grows with the square of the supply voltage. That is why lowering the voltage even a little cuts the power a lot. Because static power is nearly 0, a chip can hold billions of gates without melting. In today's very small transistors, however, leakage current trickles even through the device that is off, and this leakage has become a share that can no longer be ignored.
Back to the first screen
With the input at one end, the output sat cleanly on the opposite rail and the shoot-through hump was nearly 0. When you moved the input to the middle, the output flipped steeply and the hump briefly rose. This single graph holds both sides of CMOS. The complementary pair inverts the input cleanly, and in a stable state one side is off, cutting the path from supply to ground, so static power is nearly 0. Current flows only at the moment of flipping. This simple inverter is the brick of all digital logic, and its near-0 static power made it possible to put billions of gates on a chip that fits in your hand.
What comes next
With two transistors, the BJT and the MOSFET, you have now covered both amplification and logic. The next group takes up the operational amplifier built from these devices, together with its real limits. The first unit is the differential stage, the entrance of the op-amp. It amplifies only the difference between two inputs and suppresses noise that rides on both at once, so clean amplification starts here.