D5 · MOSFET

The CMOS Inverter: It Flips Yet Spends Almost No Power

The stage where the MOSFET changed the world is digital. Sweep the input voltage across an NMOS-PMOS pair yourself and see why the output flips cleanly while, in a stable state, almost no current flows.

Sweep the input and watch the output flip

The curve is the output voltage Vout against the input voltage Vin, the transfer characteristic. Sweep the input from 0 to Vdd. The output sits high at low input, then drops steeply in the middle. The faint bump is the through-current that flows only briefly during the transition.

Input voltage VinVin = 0.90 V

Operating point on the transfer curve

Vin = 0.90 V   →   Vout = 0.90 V

The input is near the middle. Both NMOS and PMOS are partly on, so a through-current flows briefly from Vdd to ground. The output, too, is mid-way, neither logic value.

Switching · through-current

A complementary pair, PMOS above, NMOS below

A CMOS inverter pairs two kinds of MOSFET, one above the other. On top a PMOS has its source at the supply Vdd; below, an NMOS has its source at ground. Both gates tie together to the input, both drains together to the output. The two are complementary: the NMOS turns on when its gate is high, the PMOS when its gate is low. So although they receive the same input, the two always respond oppositely.

Input 0 gives output 1, input 1 gives output 0

When the input is low (0), the NMOS is off because its gate is below threshold, and the PMOS is on because its gate is well below Vdd. The on PMOS ties the output firmly to Vdd, so the output is high (1). When the input is high (1), the opposite: only the NMOS is on, tying the output to ground, so the output is low (0). Either way, the one that is on pulls the output hard to one supply rail. So the output is a clean inversion of the input.

Almost zero static power

Here lies the magic of CMOS. In any stable state, exactly one of the two transistors is fully off. So there is simply no current path running straight from Vdd to ground. With no static current, an idle gate spends almost no power. Current flows only during the brief switching moment when the input flips, as a through-current while both devices are momentarily on, and to charge and discharge the load. So the dynamic power, P ∝ C Vdd² f, is spent only when switching. This property, that the static power is almost zero, is the foundation of digital integration, letting a single chip hold billions of gates without melting.

ObserveVin = 0 → Vout = Vdd

Input 0 gives output Vdd, that is, logic 1.

ChooseVin = 0: ? on

When input is 0, the PMOS turns on and pulls the output to Vdd.

Fill inIstatic ≈ ?

In a stable state one side is off, so the static current is almost zero.

On your ownP ∝ C Vdd² ?

Power is spent only when switching, and it scales with frequency.

Back to the first screen

With the input at one end, the output stuck cleanly to the opposite rail and the through-current bump was almost zero. Moving the input to the middle, the output flipped steeply and that bump briefly rose. That shape shows both faces of CMOS: the complementary pair inverts the input cleanly, and in a stable state one side is off, breaking the path from Vdd to ground so the static power is almost zero. Current flows only at the moment of flipping. This simple inverter is the brick of all digital logic, and its near-zero static power is what lets the chip in your hand hold billions of gates.

A CMOS inverter is a complementary pair of a PMOS (above, pulling to Vdd) and an NMOS (below, pulling to ground), with the gates tied to the input and the drains to the output. With input 0 only the PMOS is on and the output is Vdd (=1); with input 1 only the NMOS is on and the output is 0 (inversion). In any stable state one side is off, so there is no Vdd-to-ground path and the static power is almost zero. Current flows only when switching, giving the dynamic power P ∝ C Vdd² f. This near-zero static power is what made the digital integration of billions of gates possible.

What comes next

With the BJT and the MOSFET, two transistors, you have seen both amplification and logic. The next group treats the operational amplifier built from these devices, together with its real limits. Its first unit is the differential pair, the mouth of the op-amp. It amplifies only the difference of two inputs while pressing common noise down together, making the starting point of clean amplification.